1 data sheet acquired from harris semiconductor schs126d features buffered inputs typical propagation delay: 8ns at v cc = 5v, c l = 15pf, t a = 25 o c output pull-up to 10v fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh description the ?c03 and ?ct03 logic gates utilize silicon gate cmos technology to achieve operating speeds similar to lsttl gates with the low power consumption of standard cmos integrated circuits. all devices have the ability to drive 10 lsttl loads. the hct logic family is functionally as well as pin compatible with the standard ls logic family. these open drain nand gates can drive into resistive loads to output voltages as high as 10v. minimum values of r l required versus load voltage are shown in figure 2. pinout cd54hc03, cd54hct03 (cerdip) cd74hc03, cd74hct03 (pdip, soic) top view ordering information part number temp. range ( o c) package cd54hc03f3a -55 to 125 14 ld cerdip cd54hct03f3a -55 to 125 14 ld cerdip cd74hc03e -55 to 125 14 ld pdip cd74hc03m -55 to 125 14 ld soic cd74hc03mt -55 to 125 14 ld soic cd74hc03m96 -55 to 125 14 ld soic cd74hct03e -55 to 125 14 ld pdip cd74hct03m -55 to 125 14 ld soic cd74hct03mt -55 to 125 14 ld soic cd74hct03m96 -55 to 125 14 ld soic note: when ordering, use the entire part number. the suf? 96 denotes tape and reel. the suf? t denotes a small-quantity reel of 250. 1a 1b 1y 2a 2b 2y gnd v cc 4b 4a 4y 3b 3a 3y 1 2 3 4 5 6 7 14 13 12 11 10 9 8 february 1998 - revised september 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc03, cd74hc03, cd54hct03, cd74hct03 high-speed cmos logic quad 2-input nand gate with open drain [ /title ( cd74h c 03, c d74h c t03) / subject ( high s peed c mos l ogic q uad 2- i nput
2 functional diagram logic symbol truth table ab y l l z (note 1) h (note 2) h l z (note 1) h (note 2) l h z (note 1) h (note 2) hhll notes: 1. without pull-up (high impedance) 2. requires pull-up (r l to v l ) 1a 1b 2a 2b 3a 3b 4a 4b 1 2 4 5 9 10 12 13 3 6 8 11 1y 2y 3y 4y gnd = 7 v cc = 14 na nb ny cd54hc03, cd74hc03, cd54hct03, cd74hct03
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc drain current, per output, i o for -0.5v < v o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 3) ja ( o c/w) e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 maximum junction temperature (hermetic package or die) . . . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 3. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads ---------v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 2 - 20 - 40 a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v cd54hc03, cd74hc03, cd54hct, cd74hct03
4 low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd - 5.5 - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 2 - 20 - 40 a additional quiescent device current per input pin: 1 unit load ? i cc (note 4) v cc - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 4. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads na, nb 1 note: unit load is ? i cc limit speci?d in dc electrical speci?a- tions table, e.g., 360 a max at 25 o c. switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay, input to output (figure 1) t plh , t phl c l = 50pf 2 - - 100 - 125 - 150 ns 4.5 - - 20 - 25 - 30 ns 6 - - 17 - 21 - 26 ns propagation delay, data input to output y t plh , t phl c l = 15pf 5 - 8 - ----ns transition times (figure 1) t tlh , t thl c l = 50pf 2 - - 75 - 95 18 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns input capacitance c i - - - - 10 - 10 - 10 pf power dissipation capacitance (notes 5, 6) c pd - 5-6.4-----pf hct types propagation delay, input to output (figure 1) t plh , t phl c l = 50pf 4.5 - - 24 - 30 - 36 ns propagation delay, data input to output y t plh , t phl c l = 15pf 5 - 9 - ----ns transition times (figure 1) t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c i - - - - 10 - 10 - 10 pf cd54hc03, cd74hc03, cd54hct03, cd74hct03
5 power dissipation capacitance (notes 5, 6) c pd - 5-9-----pf notes: 5. c pd is used to determine the dynamic power consumption, per gate. 6. p d = c pd v cc 2 f i + (c l v cc 2 f o ) + (v l 2 /r l ) (duty factor ?ow? where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage, duty factor ?ow = percent of time output is ?ow? v l = output voltage, r l = pull-up resistor. switching speci?ations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms figure 1. transition times, propagation delay times, and test circuit figure 2. minimum resistive load vs load voltage figure 3. hc and hcu transition times and propaga- tion delay times, combination logic figure 4. hct transition times and propagation delay times, combination logic input level v s t pzl v oh output 1k ? v cc 50pf v ol 90% 10% t thl output open drain nand gate v cc nb(na) output ny t plz na(nb) v s low off low r l v l v o v cc = 5v 10% hc/hct03 v l r l r on v o 0.8v (hct v il max) 1.35v (hc v il max) r on max = 65 ? at 25 o c 4ma = 0.26v 800 700 600 500 400 300 200 100 012345678910 v l , load voltage (v) r l min, pullup resistor ( ? ) hc hct t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% cd54hc03, cd74hc03, cd54hct03, cd74hct03
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) cd54hc03f active cdip j 14 1 tbd a42 snpb n / a for pkg type cd54hc03f3a active cdip j 14 1 tbd a42 snpb n / a for pkg type cd54hct03f3a active cdip j 14 1 tbd a42 snpb n / a for pkg type cd74hc03e active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hc03ee4 active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hc03m active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc03m96 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc03m96e4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc03m96g4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc03me4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc03mg4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc03mt active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc03mte4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc03mtg4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct03e active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hct03ee4 active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hct03m active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct03m96 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct03m96e4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct03m96g4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct03me4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct03mg4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct03mt active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct03mte4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HCT03MTG4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: package option addendum www.ti.com 9-oct-2007 addendum-page 1
active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 9-oct-2007 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant cd74hc03m96 soic d 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 q1 cd74hct03m96 soic d 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 q1 package materials information www.ti.com 11-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) cd74hc03m96 soic d 14 2500 346.0 346.0 33.0 cd74hct03m96 soic d 14 2500 346.0 346.0 33.0 package materials information www.ti.com 11-mar-2008 pack materials-page 2
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